FinFETs and Multi-Sided Gate Control
A FinFET is a transistor whose conducting channel is built as a narrow, raised fin of silicon, with the gate wrapped around multiple sides of that fin. Unlike the flat, or planar, transistors used at older process generations, a FinFET lets the gate control the channel from the sides as well as from above.
That geometry matters because a transistor must do two opposing jobs: conduct a large current when it is on, and block current when it is off. As transistors shrink, the gate has more difficulty controlling the channel, so an “off” transistor leaks more. FinFETs improve the gate’s control without requiring the transistor to become wider on the chip’s surface.
The transistor a FinFET replaces
A basic MOSFET, the type of transistor used in modern digital logic, has three important regions:
- The source, where charge carriers enter.
- The drain, where they leave.
- The channel, the controllable path between them.
A gate sits over the channel. It is separated from the silicon by a very thin insulating layer, commonly called the gate dielectric or gate oxide. Applying a voltage to the gate creates an electric field through that insulator. The field changes whether the silicon beneath the gate can carry current.
For an n-channel transistor, a sufficiently high gate voltage creates a thin conducting region between source and drain. This is the transistor’s on state. With the gate voltage below the required level, the conducting region should disappear, putting the transistor in its off state.
In a planar transistor, the channel is a thin, mostly horizontal region near the top surface of the silicon. The gate controls it primarily from above. That worked well while the channel was long enough that the gate’s electric field dominated the entire region between source and drain.
Shrinking the transistor shortens the channel and brings the source and drain closer together. Their electric fields then begin to influence the channel directly. The gate no longer has exclusive control, especially near the drain. The transistor may conduct even when it is supposed to be off.
This unwanted current is called leakage. One important component is subthreshold leakage: current that flows when the gate voltage is below the normal turn-on voltage, even though the transistor is not fully on. Leakage wastes power and can heat a chip. In a large system, the leakage from billions of transistors can matter even when the processor is idle.
How the fin changes gate control
A FinFET replaces the flat channel with a narrow vertical ridge called a fin. Source and drain are formed at opposite ends of the fin. The gate crosses the fin, with an insulating dielectric between the gate material and the silicon.
The gate covers the fin’s top and its two sidewalls. The channel therefore has gate-controlled surfaces on multiple sides rather than just one. The gate does not touch the silicon directly; the dielectric still separates them. But its electric field reaches into the channel from several directions.
A simplified cross-section looks like this:
gate material
┌─────────────────┐
│ │
│ ┌─────────┐ │
│ │ silicon │ │ ← fin and channel
└───┤ fin ├───┘
└─────────┘
gate dielectric
In a real device, the gate surrounds the fin on three sides, and the source and drain extend away from the gate along the fin. The vertical sidewalls provide much of the useful channel width. A chip can also place several fins in parallel when more drive current is needed; this is analogous to making a planar transistor wider, but uses the fin’s height as well as its footprint.
The key benefit is electrostatic control—the ability of the gate’s electric field to determine the channel’s conductive state. Because the gate is close to more of the channel, its field can raise or lower the channel’s energy barrier more effectively. The source and drain have less opportunity to control the channel on their own.
Why that reduces leakage
When a FinFET is off, the gate voltage is chosen to keep a barrier in the channel. That barrier prevents most charge carriers from moving from source to drain. A gate that controls the channel from only one side has a harder time maintaining the barrier as the channel becomes short.
With a FinFET, the gate’s sidewalls help hold the barrier in place. This reduces several short-channel effects—changes in transistor behavior caused by the source and drain being too close together. One especially important effect is drain-induced barrier lowering, in which the drain’s electric field lowers the channel barrier and increases off-state current. Better surrounding control makes that lowering less severe.
The result is not zero leakage. A FinFET still has subthreshold current and other leakage paths, and its exact behavior depends on dimensions, materials, voltage, temperature, and manufacturing. But for a given performance target, the geometry generally allows a lower off-state current than a comparable planar transistor.
That improvement gives chip designers more choices. They can keep leakage low at a similar operating voltage, increase performance by allowing more drive current, or reduce voltage and save dynamic power. Dynamic power is the energy used when signals switch; FinFETs do not eliminate it, but lower supply voltage can reduce it substantially.
Where the term appears
If a process description says that a chip uses a “16 nm FinFET” or a “5 nm FinFET process,” it is referring to the transistor architecture used in that manufacturing generation. The number is a process-generation label, not necessarily the physical length of every transistor feature.
FinFETs became important when planar scaling could no longer provide enough gate control. Newer transistor designs called gate-all-around devices extend the same idea further by surrounding the channel on all sides. The underlying lesson is the same: as the channel shrinks, putting the gate closer to—and more completely around—the channel helps the gate keep the transistor off when it should be off.