Semiconductor Lithography Alignment and Overlay Budgets

20 Sep 2026 semiconductor manufacturingphysics

Alignment marks are reference features that let a lithography tool place a new circuit pattern on top of patterns already formed on a wafer. The difference between the intended and actual placement of those patterns is overlay error, and an overlay budget limits how much error each manufacturing step can contribute.

The problem: every layer must line up

A modern chip is built as a stack of patterned layers. One layer may contain transistor gates, another contact holes, and later layers may contain the metal wires that connect them. Each layer is made in a separate lithography step, often with cleaning, deposition, etching, and other processing between steps.

The wafer is not inserted into the lithography machine in exactly the same position each time. It can be shifted or rotated, and it can expand, contract, or warp slightly during processing. The machine's stage—the precision platform that moves the wafer—also has finite positioning accuracy.

Without a reference to the patterns already on the wafer, a tool could position the new pattern only relative to the wafer edge or to its own stage coordinates. That is not accurate enough. A contact could miss the transistor it must connect to, or a via—a vertical connection between metal layers—could land partly outside the wire below it.

Alignment marks solve this registration problem. Registration means placing one pattern at a known position relative to another.

What an alignment mark is

An alignment mark is a deliberately designed geometric feature, separate from the functional circuit, whose position can be detected by the lithography tool. Marks are commonly placed in the scribe lanes: narrow regions between chip-sized areas on the wafer that are later cut away.

A mark might be a set of lines, boxes, or other shapes that reflect or diffract light in a recognizable way. Some are formed in the same process as a circuit layer; others are built specifically to remain detectable through later layers. A mark from an earlier layer may become partially buried, so process engineers choose its shape, location, and detection method to keep it usable.

There are usually two relevant sets of references:

• Wafer alignment marks are features already present on the wafer. The tool measures them to learn where the existing layer actually is.
• Reticle marks are reference features on the reticle, the patterned plate that carries the design for the layer being exposed. They let the tool relate the reticle pattern to the wafer's coordinate system.

The reticle is projected onto the wafer through the lithography system's optics. In a step-and-scan tool, the system exposes one rectangular field—a repeated chip area or group of chip areas—then moves to the next field. Alignment is therefore needed both for the wafer as a whole and, depending on the process, for individual fields.

How alignment places the new layer

The sequence is easier to understand as a feedback loop:

1. The wafer is coated with photoresist, a light-sensitive material that temporarily records the new pattern.
2. The tool searches for selected alignment marks from an earlier layer.
3. Its optical or other sensing system measures each mark's position. Measuring several marks reveals not only a simple shift, but also rotation, scale changes, and wafer distortion.
4. The tool compares those measured positions with their expected coordinates and calculates corrections.
5. During exposure, the stage and reticle are adjusted so the new pattern is placed according to the corrected coordinates.
6. The resist is developed and the pattern is transferred into the wafer or a deposited material by later process steps.

A simple shift is described by two values: an error in the horizontal direction and an error in the vertical direction. Real wafers need a richer model. For example, a wafer may be slightly rotated, or its outer regions may have expanded more than its center. The alignment system fits a model to the measured marks and uses it to predict where each exposure field should go.

Alignment is not a one-time claim that the wafer is “in position.” It is a measurement followed by a positioning correction. The quality of both parts matters: a noisy mark measurement can create an incorrect correction, and a precise correction is useless if the stage or optics cannot execute it.

What overlay error means

Overlay error is the placement difference between a new layer and the earlier layer it is supposed to match. It is normally expressed as a two-dimensional displacement, such as a horizontal and vertical error, at a particular location on the wafer.

After exposure, specialized overlay metrology measures test structures—small measurement targets, usually placed in scribe lanes—on the new and previous layers. The tool compares their centers or edges and reports how far the layers are offset. This is a measurement of the result, whereas alignment is the mechanism used to prevent the error.

Overlay can include several patterns of error:

• A nearly constant shift across the wafer suggests a positioning or alignment offset.
• A rotation makes the error grow with distance from a reference point.
• A scale error makes the new layer progressively drift across the wafer.
• A field-by-field difference can indicate stage, reticle, or scanning problems.
• Local variation can come from wafer deformation or process-induced distortion.

A small overlay error may be harmless in one layer pair and fatal in another. If a large metal wire is meant to connect to a large landing area, it can tolerate more displacement than a tiny contact placed on a narrow semiconductor region.

Why processes maintain an overlay budget

An overlay budget is the maximum acceptable placement error for a layer relationship, divided among the sources that can consume it. Typical contributors include alignment measurement noise, stage positioning, reticle distortion, lens or scanner effects, wafer expansion, film stress, etching, and other process variation.

The budget exists because no single machine or measurement is perfect. It also turns a vague requirement—“the layers must line up”—into an engineering limit that equipment and process teams can test against.

For example, if a layer pair can tolerate only 10 units of overlay error, the process cannot spend all 10 on the lithography tool. Some allowance must remain for wafer distortion, metrology uncertainty, and variation from lot to lot. If independent random contributors are being combined, engineers often estimate their total using a root-sum-square calculation rather than simply adding every typical value. Systematic errors, which repeat in a predictable direction, must be modeled and corrected or added conservatively.

Exceeding the budget reduces yield: the fraction of manufactured chips that meet requirements. It can cause opens, shorts, poorly connected contacts, or transistor dimensions that vary across the wafer. Overlay numbers in a tool log, process-control chart, or excursion report therefore describe more than mechanical accuracy. They indicate whether separately manufactured layers will still form the electrical structures the design intended.