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Metastability and Two-Flop Synchronizers

electrical engineering

Metastability is a temporary state in which a digital flip-flop has not settled to a valid 0 or 1 after a clock edge. A two-flop synchronizer reduces the chance that this unsettled state reaches the rest of a digital circuit by giving it an entire clock cycle to resolve.

The problem: unrelated timing

A flip-flop is a circuit that stores one bit and updates its output at a particular transition of a clock, usually its rising edge. The clock is the repeated timing reference that coordinates state changes throughout a synchronous circuit.

For a flip-flop to capture its input reliably, the input must be stable around that clock edge:

These are properties of the flip-flop's physical circuitry, not merely rules imposed by a hardware description language.

The difficult case is a signal whose timing is not controlled by the receiving circuit's clock. Examples include a push-button input, a packet-arrival indication from another clock domain, or a status bit generated by a peripheral. Such a signal is called asynchronous relative to the receiving clock: its transition can occur at any time, including immediately before or after a sampling edge.

If the input changes inside the setup-and-hold window, the flip-flop may not be able to decide cleanly which value to store. This is a setup or hold violation. The result is not necessarily a straightforward wrong value. Instead, the internal electrical state can enter metastability.

What metastability looks like

Internally, a flip-flop uses feedback to settle on one of two stable states. One state represents 0 and the other represents 1. During metastability, that feedback is temporarily balanced: the internal voltages can sit between the normal logic levels, and the output may take an unusually long time to move to a valid level.

The final result is unpredictable. The flip-flop may resolve to 0, resolve to 1, or resolve late enough that another circuit samples an invalid or changing value. The resolution is affected by physical noise and tiny variations in the circuit, so it cannot be determined reliably from the input value alone.

Metastability is therefore not the same as ordinary digital uncertainty. A normal logic signal is expected to be either 0 or 1. A metastable output is a physical, analog condition—an intermediate electrical state in a circuit that is normally treated as digital.

A setup or hold violation does not guarantee metastability. It creates a risk of it, and the risk rises sharply as the input transition gets closer to the clock edge.

There is no fixed maximum duration that applies to every event. Most metastable states resolve quickly, but the probability of a long resolution decreases exponentially with available time. A rare event can still matter in a system that runs quickly, contains many flip-flops, or operates continuously for years.

How a two-flop synchronizer works

The standard response for a single-bit asynchronous signal is a two-flop synchronizer. Its first flip-flop samples the incoming signal. Its output is connected only to the input of a second flip-flop, and the rest of the receiving logic uses the second flip-flop's output.

On one clock edge, the first flip-flop might violate setup or hold and become metastable. The second flip-flop does not sample until the next clock edge. Between those edges, the first flip-flop has nearly one full clock period to settle to 0 or 1.

If it settles in time, the second flip-flop captures an ordinary logic value. If the first flip-flop remains metastable long enough, the second one can still be affected, but that is much less likely than the original event reaching it immediately.

The synchronizer does not make the first flip-flop immune to metastability, and it does not mathematically eliminate the possibility of failure. It reduces the probability that metastability propagates into downstream logic by adding resolution time.

The improvement is often described with mean time between failures (MTBF), an estimate of the average time between synchronizer failures under specified conditions. MTBF improves when:

The tradeoff is that the synchronized signal appears one or more clock cycles later. That latency is the cost of making an unsafe timing relationship safer.

What the circuit does and does not solve

A two-flop synchronizer is appropriate for a single bit such as an enable, mode, or level that can remain asserted long enough to be sampled. In a hardware design, the two flip-flops should be physically placed close together when possible, so routing delay does not consume the time intended for metastability resolution. Design tools commonly recognize synchronizer stages through implementation attributes, but the exact attribute name depends on the tool and device family.

It is not a general solution for transferring a multi-bit value. If each bit of a bus is synchronized independently, the bits can arrive in different cycles and form a combination that never existed at the source. It also may miss a short pulse if that pulse begins and ends between receiving-clock edges. Multi-bit data and event transfer need other protocols, such as a handshake or an asynchronous FIFO.

When a timing report mentions a CDC, or clock-domain crossing, it is referring to a signal moving between independently timed clock regions. Warnings about synchronizers, missing CDC protection, or metastability are pointing at this same physical issue: a receiving flip-flop may be asked to sample while its input is changing.

The practical rule is simple: do not feed an asynchronous signal directly into ordinary downstream logic. For a suitable single-bit signal, sample it with one flip-flop, let that result settle, and use a second flip-flop to contain the remaining metastability risk.

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